This invention relates to digital magnetic recording, and more particularly to a signal recovery technique useful for reading high density digital magnetic recordings.
The signal read from a digital magnetic recording in most storage systems is ordinarily a summation of individual pulses and is generally characterized by a some-what bell-shaped or sinusoidal-shaped pattern. The peak of each individual pulse is generally coincident with a transition of magnetic orientation on the moving magnetic media, which in turn is representative of the value of encoded digital bits. For example, a transition of magnetic orientation may occur for each xe2x80x9c1xe2x80x9d bit, whereas the absence of a transition is indicative of a xe2x80x9c0xe2x80x9d digital bit. The principal problem in the recovery of recorded information consists of detection and accurate location of the position of each individual peak. Ordinarily, a phased locked oscillator generates a series of clock signals from the pulse peaks of the read signal to establish a sequence of detection windows for reading encoded bits. Thus, a peak detected during the presence of a window indicates the digital bit value of xe2x80x9c1xe2x80x9d, whereas the absence of a peak during a detection window indicates a binary value of xe2x80x9c0xe2x80x9d.
Most prior systems employ a single channel system to detect peak positions by linearly filtering the readback signal to create a waveform with symmetric peaks. High frequency noise is rejected by band-limiting the signal. However, such systems cannot reduce intersymbol interference without decreasing the signal-to-noise ratio.
A dual channel recovery scheme is described in U.S. Pat. No. 4,517,610 a xe2x80x9cMultichannel Signal Recovery Circuitxe2x80x9d by V. B. Minuhin and assigned to the same assignee as the present invention. That system independently achieves reduction of intersymbol interference in the high resolution channel filter and good noise rejection in the low resolution channel filter. The high resolution filter provides accurate timing by boosting the high frequency content of the signal while the output of the low resolution filter provides a validation signal. By choosing an appropriate delay between the two channels, the two signals can be matched and the data latch rejects the noise-induced false crossings in the high resolution channel. The data latch is toggled by the crossover pulse of the high resolution channel following the corresponding crossover in the low resolution channel.
In addition to providing a high resolution channel which can tolerate more noise, the dual channel scheme is relatively insensitive to changes in the signal amplitude because it does not depend on a threshold detection. This feature relaxes the requirements on signal modulation due to flying height variations, media defects and media non-uniformity. Utilizing an adjustable delay line in one of the channels, it is possible to bring the two channels into optimal signal synchronization.
One problem in prior dual channel recovery circuits is the necessity to provide a very tight delay matching for different data patterns and different track radius of the magnetic data disc. The problem is made difficult by the fact that signals from different track radii of the magnetic disc are substantially different. The filters in the channels must accommodate this difference. In prior dual channel circuits, efforts to improve performance were directed toward improvement of delay matching between the channels and attempted to seek xe2x80x9caveragexe2x80x9d delay matching without correcting delays for individual bit patterns to be recovered nor for signals from different track radii.
The present invention provides a dual channel recovery circuit which is insensitive to tight delay matching between the channels. Hence, the circuit insensitive to the changes of the channel responses as the head moves from track to track along the disc radius.
It is an object of the present invention to provide a dual channel readback recovery circuit that is insensitive to tight delay matching between the channels.
Another object is to provide a dual channel readback recovery system which is insensitive to changes in track position or radius.
In accordance with the present invention, a dual channel readback recovery circuit is provided with a logical filter in the data latch to reject false crossovers that are spaced apart less than the minimal distance between written ones allowed by the code used. Polarity validation logic rejects false signals on the basis of improper polarity matching between signals in the channels of the data latch. The logical filter and validation logic prevents certain false signals from being detected as true data.
One feature of the present invention resides in the fact that the dual channel readback recovery circuit is insensitive to the delay matching between the channels, and to the changes in the channel responses as the head moves along disc radius.
Another feature of the present invention resides in the adaptation of all delays and the logical filter rejection interval to the reference clock signal which is derived from the system phase locked loop.
Still another feature of the present invention resides in the provision of an LSI (large scale integration) chip data latch with adaptation of all delays and the logical filters rejection intervals to a reference clock signal by using on-chip delay cells, thereby providing accurate control of environment and process tolerances.
The above and other features of this invention will be more fully understood from the following detailed description, and the accompanying drawings, in which:
FIG. 1 is a block diagram of a dual channel readback recovery circuit according to the presently preferred embodiment of the present invention;
FIG. 2 consisting of A through M is a timing diagram of signals at various points of the block diagrams of FIG. 1;
FIG. 3 is a diagram of a logical filter useful in the apparatus shown in FIG. 1;
FIG. 4 is a block diagram of a preferred logical filter for use in the circuit of FIG. 1;
FIG. 5 is a block diagram of a dual channel readback recovery circuit according to a modification of the present invention;
FIG. 6 A, B, D and N is a timing diagram of signals at various points of the diagram of FIG. 5; and
FIG. 7 is a block diagram of a dual channel readback recovery system according to another modification of the present invention;